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New SOC/ASIC Development assistance
- MRD and PRD analysis
- SOC/ASIC architecture specifications
- Homogeneous and Heterogeneous multiporcessor architecture
- HW/SW system partitioning
- Multibus interconnect layout and optimal system arbitration
- Bandwidth estimation and performance optimization
New CPU and Data Processing engines architecture design
- Pipelined engines
- Programmable and hardwired processing units
- ISA definition
- DSP, RISC, Vectorized, Cluster, GPU architectures
- MRD and PRD analysis
- SOC/ASIC architecture specifications
- Homogeneous and Heterogeneous multiporcessor architecture
- HW/SW system partitioning
- Multibus interconnect layout and optimal system arbitration
- Bandwidth estimation and performance optimization
New CPU and Data Processing engines architecture design
- Pipelined engines
- Programmable and hardwired processing units
- ISA definition
- DSP, RISC, Vectorized, Cluster, GPU architectures
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